Super FinSim v9.1.11 Solaris 英文正式版(仿真環境由一個附帶OVI的Virology編譯器軟體)
破解說明:
Install.
Put license.dat in any directory of your choice.
Create an environment variable called "FINTRON_LICENSE_FILE"
and set its value to the location of license.dat
Enjoy!
內容說明:
Super-FinSim 仿真環境由一個附帶OVI的Virology編譯器，一個仿真構件和一個仿真內核組成。
Verilog編譯器用於（1）檢查設計的句法和語意的正確性，（2）依據設計要求產生配置仿真內
核所要求的代碼和數據。（3）選擇性的產生一個供其它應用程式處理的中間格式表達。仿真構
件用於鏈接構成一個仿真器所需要的所有文件，例如，編譯器的輸出和仿真內核。主C鏈接器用
於此目的。仿真內核是所有Veilog設計仿真公共代碼。一旦配置完成，仿真內核就成為一個定
制的Verilog設計的仿真器。Super-FinSim的仿真器可以運行
Super-FinSim Verilog 編譯器有一個快速和強大的能進行廣泛錯誤檢查和恢復的分析器。此外，
分析器能產生標明潛在設計錯誤的警告資訊代碼，例如，交換一個越界的數組元素。
Super-FinSim Verilog 編譯器支援來自Verilog-XL的一些編譯器選項，包括控制庫搜索功能的
選項。為便於引用命令文件同樣得到支援。必需事先指定希望的Super- FinSim 仿真器模式，不
管是編譯，解釋或編譯、解釋的混合狀態。如果不指定，Super-FinSim將會試圖仿真編譯模式下
的整個設計，如果發現了一個許可的編譯仿真器，否則，將在解釋模式仿真設計。所有的編譯資
訊儲存在登記文件『finvc.log』。
Super-FinSim仿真器使用仿真內核的波形例程介面支援實時波形顯示。最近的Super-FinSim從數
據I/O的工程捕捉系統（ECS）和 Veribest』s Veriscope支援實時波形顯示。用ECS波形顯示構
造仿真器，必須指定選項『-ecs』。用Veriscope波形顯示構造仿真器，必須指定選項 『-veriscope』。
分別是Windows、Linux、Solaris平台版本。
英文說明:
Super-FinSim is the top of the line FinSim Verilog simulator. Ever since
the first FinSim Verilog simulator has been sold in 1993, the FinSim
Verilog simulators have introduced many new features that have become
state of the art in Verilog simulation: mixed Compiled and Interpreted
simulation, simulation Farm that allows one
Engineer to manage hundreds
of simultaneous simulations, separate and incremental compilation, high
performance save and restart, direct integration with C code without the
need for PLI, etc.
Super FinSim supports the entire Verilog standard IEEE 1364-1995 and
many features of IEEE 1364-2001, which are listed under Support for
Verilog 2001. It's support includes SDF, VCD, PLI, as well as excellent
integration with other tools such as a tight integration via API (for
better performance than PLI integration) with Debussy and Verdi debug
environments from Novas Software, and excellent PLI integrations with
Specman from Verisity and Vera from Synopsys for test benches, MMAV from
Denali for memory models, Undertow from Veritools for debug environment,
HDLScore from Summit Design for code coverage, and others.
In the DA Solution Limited `96 benchmark, the predecessor of
Super-FinSim, FinSim-ECS, was rated the fastest Verilog simulator.
FinSim was rated the fastest PC-based Verilog simulator in the ASIC &
EDA benchmark.
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